Nvidia(Timing Team)的笔试题目及我的答案--2006-09

出自求职百科

　　1. What major design flow steps must be accomplished to take a chip design from verified RTL code to tape out?

　　A: Synthesis -> STA -> DFT -> Package design -> Floorplan -> Place&route -> Final verification

　　分析：回答可以详细也可以简略概括，发挥的余地在第2题中，如果简略回答第1题，第2题就要详细描述

　　2. Describe in detail what occurs in each of these steps

　　A: Synthesis -> Mapping from RTL to gate level netlist with timing, area and power requirement. (not necessary to fix hold time violation)

　　STA -> Check the pre-layout netlist timing.

　　DFT -> Design for Test logic insertion which including scan, memBIST, logicBIST, JTAG

　　Package design -> package pin assignment, IO PAD allocate

　　Floorplan -> hardmacro place, power calculation and routing, routing and placement blockage definition, heretical partition if it is not flatten design.

　　Place&route -> timing and power driven placement, clock tree synthesis, SI prevented routing, setup and hold timing closure in every model

　　Final verification -> post layout STA, simulation, equivalence check, SI check, static and dynamic power analysis, EM check, DRC, LVS, and DFT test vector generation 点到为止，不答这么多也可以

　　3. In addition to the main activity occurring in each of these steps, what other types of tools/processes might you run to validate the results of each step.

　　A: Synthesis -> DC compiler or RC compiler for synthesis, Formality or Conformal for LEC

　　STA -> PT is mostly used for STA

　　DFT -> DFT compiler and Tetra-max

　　Package design -> most of them are done by in-house tools

　　Floorplan -> Encounter, Astro or Blast-Fusion, Voltage-storm or redhawk can be used for power analysis

　　Place&route -> Encounter, Astro or Blast-Fusion

　　Final verification -> Ncverilog or VCS for simulation, PT for STA, Formality or Conformal for LEC, Voltage-storm or redhawk for power analysis, CeltIc for SI, Calibre for DRC and LVS

　　凡是听说过的都可以列出来

　　前3题是考你对整个设计流程(前端+后端)的认识。现在的设计工作，即使是timing team的职位，如果对流程不够了解的话，很难同其它team的同事沟通

　　这部分是最基本的STA报告分析，除了第13题比较难以为，其余的都应该答对，不然就无法在timing team中混了

Please reference the following for the next group of questions

　　Startpoint: fifo_rd_pd_reg_16_

　　　　　　　(rising edge-triggered flip-flop clocked by my_clock)

　　Endpoint: we_bank_0_reg_2_

　　　　　　　(rising edge-triggered flip-flop clocked by my_clock)

　　Path Group: my_group

　　Path Type: max

　　Point Cap Trans Incr Path

　　------------------------------------------------------------------------------------

　　clock my_clock (rise edge) 0.0000 0.0000

　　clock network delay (ideal) 0.0000 0.0000

　　fifo_rd_pd_reg_16_/CK (p_SDFFHX4) 0.0000 0.0000 0.0000 r

　　fifo_rd_pd_reg_16_/Q (p_SDFFHX4) 0.0226 0.0542 0.1166 0.1166 f

　　obuf_U1904/Y (NAND3BX4) 0.0095 0.0643 0.0915 0.2082 f

　　obuf_U1903/Y (INVX8) 0.0188 0.0450 0.0385 0.2467 r

　　obuf_buf_1_add_524_U14/Y (NAND2X4) 0.0088 0.0431 0.0374 0.2841 f

　　U7015/Y (OAI21X4) 0.0111 0.1008 0.0781 0.3622 r

　　U22745/Y (AOI21X4) 0.0054 0.0481 0.0294 0.3916 f

　　obuf_U9743/Y (OAI21X4) 0.0067 0.0772 0.0638 0.4554 r

　　obuf_buf_1_add_524_U57/Y (XNOR2X4) 0.0098 0.1071 0.0769 0.5323 r

　　DP_OP_248_5346_8_U51/CO0 (AFCSHCINX2) 0.0037 0.0970 0.1378 0.6702 r

　　obuf_U9662/Y (MX2X4) 0.0077 0.0382 0.0825 0.7527 r

　　DP_OP_248_5346_8_U44/S (AFCSHCINX4) 0.0075 0.0462 0.1200 0.8726 f

　　obuf_U9746/Y (INVX6) 0.0174 0.0463 0.0394 0.9120 r

　　obuf_U1772/Y (NOR2X4) 0.0113 0.0554 0.0294 0.9414 f

　　U17999/Y (OA22X4) 0.0058 0.0398 0.1128 1.0542 f

　　obuf_U1852/Y (NOR2X4) 0.0116 0.0909 0.0686 1.1228 r

　　U26782/Y (INVX10) 0.0549 0.0558 0.0538 1.1765 f

　　U7011/Y (OA22X4) 0.0092 0.0465 0.0982 1.2747 f

　　U27252/Y (CLKNAND2X2) 0.0057 0.0484 0.0402 1.3149 r

　　U24494/Y (XOR2X3) 0.0058 0.0531 0.0386 1.3536 f

　　obuf_U3105/Y (NOR2X4) 0.0056 0.0583 0.0497 1.4033 r

　　obuf_U3097/Y (NAND2X4) 0.0056 0.0341 0.0329 1.4362 f

　　obuf_U3094/Y (NOR2X4) 0.0053 0.0534 0.0421 1.4784 r

　　obuf_U1886/Y (AOI21X4) 0.0157 0.0607 0.0580 1.5364 f

　　obuf_U1861/Y (NOR3X4) 0.0101 0.1561 0.1036 1.6400 r

　　U24496/Y (INVX4) 0.0073 0.0442 0.0351 1.6751 f

　　obuf_U1760/Y (OR2X4) 0.0135 0.0378 0.0731 1.7481 f

　　obuf_U9462/Y (INVX12) 0.0325 0.0428 0.0358 1.7839 r

　　U17857/Y (OAI211X4) 0.0062 0.0992 0.0506 1.8345 f

　　U24495/Y (CLKINVX6) 0.0036 0.0334 0.0188 1.8533 r

　　we_bank_0_reg_2_/D (p_SDFFRHQX4) 0.0334 0.0000 1.8533 r

　　data arrival time 1.8533

　　clock my_clock (rise edge) 1.8000 1.8000

　　clock network delay (ideal) 0.0000 1.8000

　　we_bank_0_reg_2_/CK (p_SDFFRHQX4) 0.0000 1.8000 r

　　library setup time -0.0701 1.7299

　　data required time 1.7299

　　------------------------------------------------------------------------------------

　　data required time 1.7299

　　data arrival time -1.8533

　　------------------------------------------------------------------------------------

　　slack (VIOLATED) -0.1234

　　4. What does the above information represent?

　　A: It is PT/DC timing report. It shows there is a –0.1234ns reg2reg setup violation.

　　白送分的问题

　　5. What type of tool might have produced the above report? 　　A: The report comes from Synopsys PT and DC. Encounter and other tools with STA function can create the similar report, but with different format. 　　这个问题重要吗？什么TOOL还不是都一样，关键是看懂REPORT

　　6. What is the name and frequency of the clock referenced? 　　A: Clock name is "my_clock" and frequency is 1/1.8ns 　　又一道白送分的问题

　　7. What frequency can the circuit above actually run at? 　　A: 1/1.9234ns 　　注意：不是1/1.8533ns哟，setup时间也要加上

　　8. How many levels of logic are there between the two flip-flops 　　A: 28 　　考你数数的能力哪，呵呵

　　9. What component has the greatest delay through it?

　　A: P_OP_248_5346_8_U51(AFCSHCINX2)

　　(except the flops)

　　这是考什么能力？

　　10. What is the setup time of the last flip flop in the path 　　A: 0.0701ns 　　问题描述得太不专业了，应该是： 　　What is the setup requirement of the capture flip flop in the path

　　11. What is the hold time of the last flip flop in the path 　　A: There is no information about hold time in this report. 　　陷阱

　　12. What assumptions can you make about operating conditions from this report? 　　A: Worst Case 　　Best Case也有可能

　　13. Would this report be useful near the end (tape-out) of a chip? Please explain your answer.

　　A: No. The main reason is clock insertion delay was not in the report.

　　--> clock network delay (ideal)

　　We can guess either the report came from pre-layout netlist, or wrong STA setting if from post-layout netlist.

　　这是个有水平的问题，答对者大有希望进入第二轮面试

　　如果是我出题，就把那几个白送分的题目去掉，换上分析setup violation原因的问题，当然，不能用现在这个timing report

　　Please use the following diagram for the next questions (14，15，16)

　　这部分是考setup和hold的概念，问题的特点是在时钟net上多了一个buf，这样的问题在post-layout的STA中很常见 问题看着复杂，其实有一个捷径，只要比照part 2/5中的timing report，很快就能找到答案

　　14. What parameters do you need to know to calculate the timing of the above circuit?

　　A: All following max and min delay information is requested.

　　　　Flop A: ck->Q

　　　　Logic : input -> output

　　　　Buffer : input -> output

　　　　And

　　　　flop B: setup and hold timing requirement.

　　　　Clock: period and uncertainty

　　不要忘记时钟周期

　　简单地说，“要全部timing information”，如果真这么答了，不知考官给不给分

　　15. Using the parameters from #14, write the equation that needs to be fulfilled in order for the above circuit to meet setup time on Flop B. Assume parameters are max delay. 　　A: clock(period) + Buffer(delay) – flopB(setup) - clock(uncertainty) >= flopA(ck->Q) + logic(delay)

　　16. Using the parameters from #14, write the equation that needs to be fulfilled in order for the above circuit to meet hold time on Flop B. Assume parameters are min delay. 　　A: FlopB(hold) + Buffer(delay) <= flopA(ck->Q) + logic(delay)

　　Please use the following diagram for the next questions (17，18)

　　再加一条path和一个input，同part 3/5比难度也没有增加

　　17. What new parameters do you need to know to calculate the timing of the above circuit?

　　A: And: max and min delay

　　　　SignalX: max and min input delay

　　18. Are there new issues that are of concern with the addition of the new gate and input signal? Please describe in detail 　　A: need to check setup and hold timing for flopA using And gate and Signal X input delay. The setup and hold timing for FlopB should be verified again because the change of output loading at FlopA Q pin.

　　注意：flopA的负载的增加会引起flopA到flopB之间path delay的变化，一般会被初学者忽略

　　不解释了，大家都知道，异步通信的经典

　　19. What is metastability and why is it problematic?

　　A: Metastability is a term to describe the data can't be transferred successfully between asynchronous clock domain.

　　20. What techniques can you use to prevent metastability?

　　A: double flops

　　总在来讲，考题不难，只有13和18要些经验，答对这2道的应该被列为下一轮的重点考虑对象。其它的题如果答错3道以上，基本就歇菜了。